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Integrated Circuit Systems, Inc.
ICS85357I-01
4:1 OR 2:1 DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
FEATURES
* High speed differential multiplexer. The device can be configured as either a 4:1 or 2:1 multiplexer * 1 differential 3.3V LVPECL output * 4 selectable CLK, nCLK inputs * CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * Maximum output frequency: 750MHz * Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLKx input * Part-to-part skew: 415ps (maximum) * Propagation delay: 1.5ns (maximum) * LVPECL mode operating voltage supply range: VCC = 3.135V to 3.465V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -3.135V to -3.465V * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS85357I-01 is a 4:1 or 2:1 Differential-to3.3V LVPECL / ECL clock multiplexer which can HiPerClockSTM operate up to 750MHz and is a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS85357I-01 has 4 selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The device can operate using a 3.3V LVPECL (VEE = 0V, VCC = 3.135V to 3.465V) or 3.3V ECL (VCC = 0V, VEE = -3.135V to -3.465V). The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The select pins have internal pulldown resistors. Leaving one input unconnected (pulled to logic low by the internal resistor) will transform the device into a 2:1 multiplexer. The SEL1 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 00 selects CLK0, nCLK0).
ICS
BLOCK DIAGRAM
CLK0 nCLK0 CLK1 nCLK1 CLK2 nCLK2 CLK3 nCLK3 00
PIN ASSIGNMENT
VCC CLK0 nCLK0 CLK1 nCLK1 CLK2 nCLK2 CLK3 nCLK3 VEE 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC SEL1 SEL0 VCC Q0 nQ0 VCC nc nc VEE
01
Q0 nQ0
10
11
ICS85357I-01
SEL1 SEL0
20-Lead TSSOP 4.40mm x 6.50mm x 0.90mm body package G Package Top View
85357AGI-01
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REV. A NOVEMBER 11, 2004
Integrated Circuit Systems, Inc.
ICS85357I-01
4:1 OR 2:1 DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
Type Power Input Input Input Input Input Input Input Input Power Unused Output Input Input Pulldown Pulldown Pulldown Pullup Pulldown Pullup Pulldown Pullup Pulldown Pullup Description Positive supply pins. Non-inver ting differential clock input. Inver ting differential clock input. Non-inver ting differential clock input. Inver ting differential clock input. Non-inver ting differential clock input. Inver ting differential clock input. Non-inver ting differential clock input. Inver ting differential clock input. Negative supply pins. No connect. Differential output pairs. LVPECL interface levels. Clock select input. LVCMOS / LVTTL interface levels. Clock select input. LVCMOS / LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 14, 17, 20 2 3 4 5 6 7 8 9 10, 11 12, 13 15, 16 18 19 Name VCC CLK0 nCLK0 CLK1 nCLK1 CLK2 nCLK2 CLK3 nCLK3 VEE nc nQ0, Q0 S E L0 S E L1
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
TABLE 3. CONTROL INPUT FUNCTION TABLE
Inputs SEL1 0 0 1 1 S E L0 0 1 0 1 Clock Out CLK CLK0, nCLK0 CLK1, nCLK1 CLK2, nCLK2 CLK3, nCLK3
85357AGI-01
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REV. A NOVEMBER 11, 2004
Integrated Circuit Systems, Inc.
ICS85357I-01
4:1 OR 2:1 DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 73.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5%, TA= -40C TO 85C
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 35 Units V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V5%, TA= -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current SEL0, SEL1 SEL0, SEL1 SEL0, SEL1 SEL0, SEL1 VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V -5 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 Units V V A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V5%, TA= -40C TO 85C
Symbol Parameter CLK0, CLK1, CLK2, CLK3 Test Conditions VCC = VIN = 3.465V Minimum Typical Maximum 150 5 Units A A A A 1.3 VCC - 0.85 V V
nCLK0, nCLK1, VCC = VIN = 3.465V nCLK2, nCLK3 CLK0, CLK1, -5 VCC = 3.465V, VIN = 0V CLK2, CLK3 IIL Input Low Current nCLK0, nCLK1, VCC = 3.465V, VIN = 0V -150 nCLK2, nCLK3 V PP Peak-to-Peak Voltage 0.15 Common Mode Input Voltage; VCMR VEE + 0.5 NOTE 1, 2 NOTE 1: Common mode input voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is VCC + 0.3V.
IIH
Input High Current
85357AGI-01
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REV. A NOVEMBER 11, 2004
Integrated Circuit Systems, Inc.
ICS85357I-01
4:1 OR 2:1 DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC -1.7 1.0 Units V V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V5%, TA= -40C TO 85C
Symbol Parameter VOH VOL VSWING Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V5%, TA= -40C TO 85C
Symbol fMAX t PD Parameter Maximum Output Frequency Propagation Delay; NOTE 1 Par t-to-Par t Skew; NOTE 2, 3 Output Rise/Fall Time 20% to 80% 200 1 Test Conditions Minimum Typical Maximum 750 1.5 415 700 Units MHz ns ps ps %
tsk(pp)
tR / tF
odc Output Duty Cycle 46 54 NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
85357AGI-01
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REV. A NOVEMBER 11, 2004
Integrated Circuit Systems, Inc.
ICS85357I-01
4:1 OR 2:1 DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
2V
V CC
Qx
SCOPE
V CC
LVPECL
VEE
nQx
nCLK0: nCLK3 V CLK0: CLK3 VEE
PP
Cross Points
V
CMR
-1.3V -0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1 nCLK0: nCLK3 CLK0: CLK3 nQ0 Q0
Qx PART 2
Qy
tsk(o)
tPD
PART-TO-PART SKEW
PROPAGATION DELAY
nQ0 80% Clock Outputs 80% VSW I N G 20% tR tF 20% Q0
Pulse Width t
PERIOD
odc =
t PW t PERIOD
OUTPUT RISE/FALL TIME
85357AGI-01
OUTPUT DUTY CYLE/PULSE WIDTH/PERIOD
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5
REV. A NOVEMBER 11, 2004
Integrated Circuit Systems, Inc.
ICS85357I-01
4:1 OR 2:1 DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input
CLKx
V_REF
nCLKx
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
Zo = 50
3.3V 125 125
FOUT
FIN
Zo = 50
Zo = 50
FOUT
50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FIN
Zo = 50 84 84
RTT =
FIGURE 2A. LVPECL OUTPUT TERMINATION
85357AGI-01
FIGURE 2B. LVPECL OUTPUT TERMINATION
REV. A NOVEMBER 11, 2004
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Integrated Circuit Systems, Inc.
ICS85357I-01
4:1 OR 2:1 DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
3.3V
Zo = 50 Ohm
LVDS_Driv er
CLK
R1 100
nCLK
Receiv er
Zo = 50 Ohm
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
R3 125
R4 125
CLK
Zo = 50 Ohm
C2
nCLK
HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
85357AGI-01
BY
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REV. A NOVEMBER 11, 2004
Integrated Circuit Systems, Inc.
ICS85357I-01
4:1 OR 2:1 DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85357I-01. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS85357I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 35mA = 121.3mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 1 * 30mW = 30mW
Total Power_MAX (3.465V, with all outputs switching) = 121.3mW + 30mW = 151.3mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.151W * 66.6C/W = 95.05C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
20-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85357AGI-01
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REV. A NOVEMBER 11, 2004
Integrated Circuit Systems, Inc.
3. Calculations and Equations.
ICS85357I-01
4:1 OR 2:1 DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CC_MAX
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
85357AGI-01
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REV. A NOVEMBER 11, 2004
Integrated Circuit Systems, Inc.
ICS85357I-01
4:1 OR 2:1 DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
20 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85357I-01 is: 400
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REV. A NOVEMBER 11, 2004
Integrated Circuit Systems, Inc.
ICS85357I-01
4:1 OR 2:1 DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
20 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 Millimeters Minimum 20 1.20 0.15 1.05 0.30 0.20 6.60 Maximum
Reference Document: JEDEC Publication 95, MO-153
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REV. A NOVEMBER 11, 2004
Integrated Circuit Systems, Inc.
ICS85357I-01
4:1 OR 2:1 DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
Marking Package 20 lead TSSOP 20 lead TSSOP on Tape and Reel Count 74 per tube 2500 Temperature -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS85357AGI-01 ICS85357AGI-01T ICS85357AI01 ICS85357AI01
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial or industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85357AGI-01
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REV. A NOVEMBER 11, 2004

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